Engine timing computer

ABSTRACT

There is disclosed a method and apparatus for internal combustion engine timing based on measurement of the advance or retard of the firing of each spark plug with respect to a reference derived from the top dead center position of the piston for the number one cylinder. The engine timing is adjusted so that the average value of the advance or retard for all plugs equals a predetermined design value. A variable frequency oscillator is phase-locked by signals representing individual spark plug firing to operate at a frequency of 3,600 pulses per engine revolution. A reference related to the top dead center position of piston for the first cylinder is determined by sensing a notch in the engine damper or fan pulley, and is used to produce a series of pseudo damper pulses offset from the top dead center positions of the various pistons by 45 degrees by dividing the output of the variable frequency oscillator and selecting pulses to define the pseudo damper pulse interval based on the number of cylinders in the engine being timed. Timing measurement is achieved by counting the number of pulses between firing of a plug and the associated pseudo damper pulse over several complete engine operating cycles, averaging the result and removing the 45 degree offset. Digital display, printout, upper and lower limit computation and actual engine RPM measurements are also provided.

' Elnited States Patent 91 Abnett et al.

[ ENGINE TIMING COMPUTER [75] Inventors: Albert C. Abnett, Westerville;

Robert A. Boley, Columbus, both of Ohio [73] Assignee: Autech, Inc.,Columbus, Ohio [22] Filed: Jan. 20, 1972 [21] Appl. No.: 219,250

[52] 11.8. CI. 324/16 R, 73/118 [51] Int. Cl. F02p 17/00 [58] Fleld ofSearch [56] References Cited UNITED STATES PATENTS 3,454,871 7/1969Nolting 324/16 3,474,667 10/1969 Fuchs 324/16 FOREIGN PATENTS ORAPPLICATIONS 249,849 8/1969 U.S.S.R 324/16 Primary ExaminerMichael J.Lynch Attorney-Robert E. LeBlanc et al.

[57] ABSTRACT There is disclosed a method and apparatus for internal 1Oct. 23, 1973 combustion engine timing based on measurement of theadvance or retard of the firing of each spark plug with respect to areference derived from the top dead center position of the piston forthe number one cylinder. The engine timing is adjusted so that theaverage value of the advance or retard for all plugs equals apredetermined design value. A variable frequency oscillator isphase-locked by signals representing individual spark plug firing tooperate at a frequency of 3,600 pulses per engine revolution. Areference related to the top dead center position of piston for thefirst cylinder is determined by sensing a notch in the engine damper orfan pulley, and is used to produce a series of pseudo damper pulsesoffset from the top dead center positions of the various pistons by 45degrees by dividing the output of the variable frequency oscillator andselecting pulses to define the pseudo damper pulse interval based on thenumber of cylinders in the engine being timed. Timing measurement isachieved by counting the number of pulses between firing of a plug andthe associated pseudo damper pulse over several complete engineoperating cycles, averaging the result and removing the 45 degreeoffset. Digital display, printout, upper and lower limit computation andactual engine RPM measurements are also provided;

33 fill? Prsrhaliee United States Patent [191 Abnett et al.

[ Oct. 23, 1973 OATAPER 22 T0 PRINTER I00 P'CKUP DAMPER L l 34 36 56SIGNAL I FAULT FAULT l4 PROCESSOR 39w DETECTION m 26 C'Rclm INDICATORSPARK 24 42 PICKUP SPARK SIGNAL v00 28 PROcEssOR 4e PHASE DIVIDER aDETECTOR 40OA2OO/IROO L 4 i I GENERATOR E Msz L58 6O 4 6 HI 64 f 68 76TOLERANCE AOv/RET sEOOENOTNO COUNT T m LOGIC LOGIC GENERATOR 92 TARGET90 7B COUNT OENERATOR E70 1 AvERAOTNO MAIN v COUNTING OONPARlsON LOG'CLOGIC LOGIC t T J E as s CALIBRATION MN OOONT 94 l OENERATOR LIMIT RPMLOGIC i cOuNTER $82 I RPN LIMIT TIMINGANGLE 96 E DISPLAY LIMIT RPM soDISPLAY 98 DISPLAY i L84 H OuTPuT T A PRINTER UNIT FROM '00 FAULT 4DETECTION CIRCUIT 34 PATENTED N 23 Ian 3.768.004 SHEET 10$ 8 DAMPER 22TO PRINTER IOO PICKUP DAMPER l 34 J 36 5s g gg ggg TINT AM A I 39DETECTION a 2s 2/ CIRCUIT INDICATOR ADv/RET SPARK Q24 4 END; 42 8 PICKUPSPARK 40 g SIGNAL I TACH v00 28 PROCESSOR N 38 Q 46 44 4 D PHASE 7DIVIDER s DETECTOR .400/200/[800 W N 4 61 8f GENERATOR SELECT0R\62 L586O T4 6 8i 48 4 L w /68 TOLERANCE ADv/REI SEQUENCING COUNT LOGIC LDOIOGENERATOR r92 ADv/RET M TARGET eo 7 COUNT 72 GENERATOR I l I AvERAsINDMAIN PA COUNTING V COM LOGIC LOGIC LOGIC J g9 88 L L CALIBRATION v I 941 74/ COUNT GENERATOR LIMIT RPM LOGIC COUNTER p82 RPM LIMIT TIMING ANGLEm 96 SET E DISPLAY LIMIT RPM 80 DISPLAY DIsPLAY *P L84 OIITPIIT FIG. MPRINTER uNIT FROM PAIILT N DETEOTION CIRCUIT 34 minnow 23 ms 30% E i wwm 39w T D N 9-H n E? gm 3 .232 1 E080 2N m2: 9 1 $8M 28m J I 5 g r A? Eo m FAA 05 I $538 a M239 Sm g m I? E m M383 8 Na m ET m 5 H s E 3 3 3m82 u m H 1 g N 2% ma 3: oww f m at Na 88 A 3 Ems AZ; Q E so; 5 mm @M m b8? am X N v Na Na v as 0 E ENGINE TIMING COMPUTER INTRODUCTION Thisinvention relates to internal combustion engine timing, and moreparticularly to techniques and equipment for improving the accuracy oftiming of engines such as automobile engines both in the assembly plant,and thereafter for purposes of routine maintenance.

Reference is made to a related patent application, Ser. No. 219,416filed Jan. 20, 1972 entitled Engine Timing Computer, filed concurrentlyherewith in the name of Arthur R. Crawford et al, which applicationclaims certain subject matter disclosed herein, and related to thesubject matter claimed in this application.

BACKGROUND Briefly, by way of background, in a four-cycle engine of thetype customarily employed in automobiles, each cylinder fires once forevery two revolutions of the crankshaft. In most engines, a spark isprovided for each cylinder slightly prior to the top dead centerposition for the piston on its compression stroke, although engines areoccasionally designed to fire after the top dead center position.

Firing is controlled by a timing system. This includes a distributorhaving a rotating shaft coupled to the crankshaft by a 2:1 reductiongearing mechanism whereby the distributor shaft makes one completerotation for every two crankshaft rotations. The distributor shaftcarries a multi-lobe cam, (one lobe for each cylinder) which engageswith a follower to operate a set of breaker points. These are shunted bya capacitor in a primary circuit of a spark coil connected to thebattery. Opening of the points as the timing cam rotates provides rapidmagnetic field changes in the secondary of the spark coil with resultinghigh voltage across the coil secondaries. The high voltage pulses arecoupled to individual spark plugs by a rotating contact member carriedby the distributor shaft and engaging with a series of fixed contacts inthe distributor, each connected to one of the spark plugs.

Timing is normally adjusted in relation to the top dead center positionof the number one piston by rotating a plate carrying the cam followerand breaker points in relation to the cam on the distributor shaft.

Accurate engine timing is extremely important because an improperlytimed engine operates inefficiently and with less than optimum power andalso, because timing errors increase the octane requirement of the fuel.Also of. increasing importance is the fact that an improperly timedengine produces high exhaust emissions and-consequent air pollution.

The normal procedure employed in engine timing utilizes a timing lightwhich is a stroboscopic lamp fired by discharge of the number one sparkplug. Firing of the lamp illuminates a pointer mounted on the engine inrelation to a dial on the rotating damper pulley. The recurringmomentary illumination of the pointer and dial indicates therelationship between the firing of the No. 1 cylinder and the top deadcenter position of its piston, ordinarily in terms of degrees before (orafter) top dead center.

The foregoing system possesses several disadvantages. First, because ofthe positioning of the various measuring components, there can besubstantial and unpredictable parallax in reading of the pointer andmarkings on the damper pulley, thereby rendering the measurementinaccurate. Moreover, the stroboscopic timing equipment itself possessesinherent inaccuracies, due to the dynamic nature of the operation, andthe visual nature of the observations. Further, measurements have beenmade with reference to a single cylinder on the assumption that eachcylinder actually fires in precisely fixed relationship to the No.1cylinder. However, imperfections in the timing gears, the cam, andelsewhere in the timing mechanism can cause deviation of as much as plusor minus 3 degrees from the design values. Thus, if the cam surface forcylinder NO.l is inaccurate, the resulting offset may completelyinvalidate the timing reading. Even if the NO.l cylinder is adjusted tofire exactly as specified, for example, at 6 degrees before top deadcenter, adjustment of the timing for the N01 cylinder to achieve thisordinarily results in firing of the remaining cylinders anywhere between3 and 9 degrees before top dead center. This is totally unacceptable,particularly in view of increasing demands for reudced exhaustemissions.

For the foregoing reasons, several other techniques have been proposedto improve the accuracy of the engine timing operation, mostly involvingelectronically measuring the time interval between the firing and thetop deadcenter position of the associated cylinder. Equipment of thistype can provide a more accurate measurement of the timing angle for aparticular cylinder, but totally fails to overcome the problem notedabove regarding imperfection in the timing mechanism and its effect onthe relationship between the firing angles for thecylinders.

Evidently, in recognition of the foregoing, it has been proposed tomeasure the timing angle for each cylinder with respect to the top deadcenter position of its respective piston, and to adjust the distributorrotor until the average of all of the angles equals the design value asspecified with respect to cylinder NO. I. The general concept of averagetiming appears to have excellent prospects as a means of improvingengine efficiency and reducing exhaust emissions. However, theheretofore proposed implementation of the average timing concept knownto applicant appears to be subject to several important disadvantages.

For example, average timing as heretofore proposed employs a fixedfrequency reference oscillator and provides a measurement by countingthe number of reference oscillator pulses between firing of eachcylinder and a control signal representing the top dead center positionfor each cylinder. Since the frequency of the oscillator must bear apredetermined relation to the engine RPM at the time the measurement ismade, means are provided to inhibit measurement unless the engine isrunning at the proper RPM. This presents difficulties since maintaininga constant engine RPM over even one revolution is almost impossible.While the variation in engine speed over a single revolution may not begreat, nevertheless, even small changes ths substantial inaccuracy.twenty-eighth ths For example, if theRPM at the time of measurement isas little as 2 percent high, a timing error exceeding the required plusor minus 0.1 degree accuracy will occur. For this reason, successfulaveeraging has been found to require measurement of timing angles overseveral engine revolutions, which does not appear practical with theprior equipment.

Another difficulty with the heretofore proposed average timing techniqueis the necessity for providing a pulse corresponding to the top deadcenter position for each cylinder. This is proposed to be accomplishedin several way, for example a star wheel, or cam, or the like can bemounted on the front of the damper pulley, and an appropriate sensormounted in fixed relationship on the engine. Alternatively, notches orthe like could be cut directly in the damper pulley for interaction witha proximity sensor. Both of these techniques possess a significanteconomic disadvantage and in fact substantial resistance has beenencountered in the industry. Placement of even a second notch on thedamper pulley, i.e., for four-cylinder engine, is re garded aseconomically unattractive, and its use has been discouraged by themanufacturers.

A further problem with the previously proposed system is that undercertain circumstances an engine designed to fire before top dead centermay occasionally appear to fire after top dead center for a particularcylinder. The exact cause of such cross-over error is not clear but itis thought to be caused, for example, by a backfire, faulty plug, orother similar factors causing drastic transient changes in engine speed.Another possible cause may be inherent tracking imperfections in themeasuring circuitry, though this may be more likely where, as describedbelow, a constant number of pulses per engine revolution is employed. Inany case, if logic circuitry designed to begin counting upon firing ofthe engine and to stop counting in response to the top dead center pulseis used under such circumstances, it will be appreciated that the countwill begin with the engine firing but the top dead center pulse havingalready passed, the counting circuitry will continue to run until thenext top dead center pulse. Even on an average basis, the resultingmeasurement would be so seriously affected as to be meaningless.

Yet an additional difficulty with the previously proposed device foraverage timing is its apparent inability to operate in the retard mode,as well as in the advance mode, without substantial inconvenience andpossible unreliability. This presents a definite lack of flexibility.

BRIEF DESCRIPTION OF THE INVENTION The present invention seeks to avoidboth the technical and economic problems with the heretofore proposedaverage timing techniques by employment of a system including a variablefrequency oscillator for generating a fixed number of counting pulsesper engine revolution, (preferably 3,600 so each pulse represents 0.1degrees) and by averaging over several engine operating cycles, thenumber of pulses between the firing of each spark plug and the top deadcenter position for that cylinder, but based on a reference keyed to topdead center for the NO.l cylinder. Elaborating on the foregoing, byusing a fixed number of pulses per revolution, the time scale formeasurement is automatically expanded or contracted to conform to engineRPM. By making all measurements with reference to the top dead centerposition for the No.1 cylinder, the need for generating pulsescorrespnding to the top dead center position of the other cylinders isavoided and with it, the economic diasdvantages of providing more thanone notch or other indicator.

To eliminate the need for actually counting with respect to the top deadcenter position of the first cylinder, there is provided means forgenerating a series of pseudo damper pulses. This operates to count theoscillator pulses, and to provide reference pulses at predeterminedintervals in accordance with the number of cylinders in the engine beingtimed. For example, for a four-cy1inder engine, and with 3,600 countingpulses per revolution, the pseudo damper pulses would be spaced 1,800counting pulses apart. correspondingly, pseudo damper pulses for six andeight-cylinder engines would occur at 1,200 and 900 pulse intervals,respectively.

Aside from the economic advantages mentioned above, employment of pseudodamper pulses has two additional advantages. First, it permitsmeasurement of the position of a notch in the damper (or fan pulley) asa reference in arbitrary relationship to the top dead center positionfor the No.1 cylinder. Thus, if it proves to be convenient to positionthe proximity detector in such a manner that the notch passes thedetector degrees before top dead center for the No.1 cylinder, locationof the actual top dead center position may be accomplished simply bycounting 1,000 pulses following the pickup output.

More importantly, since the reference position is arbitrary, a timingangle of 6 degrees before top dead center is equivalent to an angle of16 degrees before a reference 10 degrees after the top dead center. Thisfact, and the fact that establishment of a reference is a simple matterof counting the desired number of pulses after the damper notch issensed, completely avoids the possibility of a cross-over error.

Specifically, the reference for cylinder No. 1 is chosen to be 45degrees before top dead center for timing an engine designed to fireafter top dead center (retard mode) and at 45 degrees after top daedcenter for timing an engine designed to fire at or before top deadcenter (advance mode.)

The actual timing measurement is made by counting the number of variablefrequency timing pulses between ignition of a cylinder and theassociated pseudo damper pulse. This is accomplished by a counteractivated either by the pseudo damper pulse for retarded firing or bythe ignition pulse for advanced firing, and turned off by the ignitionpulse for advanced firing.

The averaging operation is accomplished by maintaining a running countfor the required number of ignitions. To reduce the required countcapacity, the output of the reference clock is divided by the number ofignitions over which the average is taken before being coupled throughthe gating circuit to the counter.

The result is displayed digitally with the least significant figurebeing 0.1 degrees. The 45 degree offset mentioned above is subtractedout prior to display.

Additional features of the invention include means for accuratelylocating the damper reference notch means for providing upper and lowerlimit indications with respect to the target timing angle, engine RPMreadout, and means to provide an indication when the RPM exceeds a setlimit. The system also includes fault detection means for providing anindication of system inoperativeness and an output printer, by which apermanent record of the timing operation can be produced.

Accordingly, among the objects of this invention are the following:

10 provide improved techniques and apparatus for internal combustionengine tinfin g f To provide such techniques and apparatus utilizingaverage timing concepts but not subject to the disadvantages ofheretofore proposed techniques;

To provide techniques and apparatus for average engine timing based onmeasurement of the angular interval between the ignition spark for eachcylinder, and a reference angular position based on the top dead centerposition for the first cylinder;

To provide such average timing techniques and apparatus in which theaverage is taken over several com- 7 plete engine cycles to compensatefor nonuniformities of engine speed;

To provide average timing equipment and techniques utilizing a variablefrequency oscillator adapted to produce a constant number of pulses perengine revolution and means for counting the number of pulses betweenignition for each cylinder and a reference angular position based on thetop dead center position for cylinder No. 1;

To provide such a system in which the variable frequency oscillator isphase-locked with the engine ignition pulses;

To provide average engine timing techniques and apparatus as describedabove in which the reference angular position is established bygeneration of a series of pseudo damper pulses at predetermined angularinterval in relation to top dead center for cylinder No. 1;

To provide such pseudo damper pulses by selecting ones of the outputpulses of the variable frequency oscillator at fixed intervalsdetermined by the number of cylinders in the engine with the first ofsaid pulses being related to the top dead center position for the firstcylinder;

To provide average timing techniques and equipment as described above inwhich the reference position for cylinder No. l is a predeterminednumber of degrees before or after top dead center for said cylinder;

To provide average techniques and apparatus as described above in whichthe reference position is determined by a marker rotatable with theengine crankshaft, and a fixed sensor positioned to provide an outputsignal in response to passage of the marker and in predetermined angularrelation to the top dead center position for the first cylinder;

To provide internal combustion engine timing techniques and apparatus asdescribed above in which the average engine timing is determined byestablishing a predetermined number of counting intervals representingthe desired multiple of the number of cylinders over which the avarageis to be taken, generating a series of measuring pulses, the number ofsuch pulses per engine revolution being constant, dividing the series ofmeasuring pulses by the number of counting intervals, establishing aseries of measuring intervals between ignition for a particular cylinderand a reference based on the top dead center position for one of thecylinders, counting the number of divided counting pulses for a numberof measuring intervals equal to said predetermined number and displayingthe result as the average timing of said engine; and

To provide average timing techniques and apparatus as described above inwhich the reference position with respect to the one cylinder isestablished by producing a reference pulse in known angular relationshipto the top dead center position for that cylinder, dividing the pulsetrain to produce a series of pseudo reference pulses per revolutionequal in number to one-half the number of cylinders, and using the sogenerated pseudo reference pulses in defining the succession of countingintervals.

The exact nature of this invention as well as other objects andadvantages thereof will become apparent from consideration of thefollowing detailed description together with the drawings in which:

FIG. 1 is an overall block diagram showing the organization of apreferred embodiment of the invention;

FIGS. 2a-2i are waveform diagrams pertinent to the operation of certainportions of the system of FIG. 1;

FIGS. 3 through 6 show the circuit diagrams for the damper signalprocessor, the spark signal processor, the tachometer unit, and thephase locked loop shown in FIG. 1;

FIG. 7 is a circuit diagram of the pseudo pulse generator and digitaldelay units shown in FIG. 1;

FIG. 8 is a circuit diagram of the main counting logic, theadvance-retard logic, the averaging logic, the RPM computing logic, andthe timing angle and RPM display units;

FIG. 9 is a circuit diagram of the calibration and tolerance countgenerators, and the sequencing logic unit; and

FIG. 10 is a circuit diagram of the comparison and limit logic units,the RPM limit setting unit, and the limit display.

Referring now to FIG. 1, there is shown in blockdiagram form a preferredembodiment of the engine timing apparatus of this invention. The system,generally denoted at 12, may be regarded as comprised of four relatedsub-systems, namely a timing signal generating unit 14, a timingcomputer 16, an RPM' computer 18, and an RPM and timing limit computer20. The timing signal generator, illustrated in the upper half of FIG.'1 is comprised of input signal processors 22 and 24 for the dampernotch pickup 26 and the spark coil pickup 28, a phase-locked loop 30 forgenerating a variable frequency pulse train comprising 3,600 pulses perengine revolution, and a pseudo damper pulse generator 32 which operatesto select desired ones of the 3,600 pulses per revolution and to providethese as synthetic damper notch pulses in proper time relationship totheactual damper notch pulse provided by pickup 26.

Pickups 26 and 28 are constructed in any suitable fashion. Damper pickup26 is preferably an eddy current or other magnetic field sensitivedevice while spark pickup 28 is either magnetic field or electric fieldsensitive (capacitive) as desired. The damper pickup operates as aproximity sensor to produce an output signal once per revolution of thedamper as a notch cut in its periphery passes through the pickup fieldof view. Tothis end, there is advantageously provided a mounting fixture(not shown) on the engine to support the pickup in suitable relation tothe damper so that the pickup senses the notch as the damper rotates.The mounting fixture itself may be of any suitable construction,- anddoes not constitute part of this invention as such. However, it will berealized that placement of the fixture will depend on availability of anaccessible mounting space. Any suitable mounting position may beemployed, as long as the exact relationship between passage of thedamper notch through the pickup field of sensitivity and the top deadcenter position for one of the pistons (for example, piston No. l) isaccurately known. In this connection, the system can readily accommodateany angular relationship between the position at which the damper notchis sensed and top dead center for the No. 1 piston. However, forsimplicity, the following description assumes that the damper notch issensed by pickup 26 exactly 135 degrees after piston No. 1 reaches itstop dead center position. system adjustment to accommodate otherpositions is explained below.

Damper signal processor 22 converts the pickup output into a narrowpulse defining the center of the damper notch and thereby provides aprecise reference for generation of a series of pseudo damper pulsesfrom which timing measurement is actually made. The output of the dampersignal processor is also coupled to a fault detection circuit 34 whichoperates an indicator 36 in the event of signal loss from the damperpickup.

Spark pickup 28 operates to provide a signal representing the magneticfield pattern associated with the spark coil output. In one preferredconstruction, the spark pickup is constructed to fit around the sparkcoil output wire, in the manner of a clip on type ammeter, but otherconstructions may also be employed, if desired.

Spark signal processor 24 responds to the pickup output to generate apulse in precise time relationship with the opening of the distributorpoints. This signal is used directly by timing computer 16, and is alsoprovided to a tachometer 38 which produces an analog signalrepresentative of the frequency of the spark pickup output. Generationof the tachometer output is accomplished by integrating the series ofpulses produced by spark signal processor 24. However, because afourcylinder engine produces two spark pulses per revolution as comparedto three spark pulses per revolution for a six-cylinder engine and fourspark pulses per revolution of an eight-cylinder engine, tachometer 34includes means to convert each of the incoming pulses from spark signalprocessor 24 into a pulse of different width in accordance with thenumber of cylinders in the engine. To this end, there is provided athreeposition switch 39 which activates timing circuitry hereinafterdescribed such that the pulse width for a six-cylinder engine istwo-thirds the pulse width for a four-cylinder engine, while the pulsewidth for an eightcylinder engine is one-half the pulse width for afourcylinder engine.

The tachometer output is provided as a second input to fault detectioncircuit 34 which operates indicator 36 if the spark signal is lost. Theoutput of tachometer also provides a control input for phase-locked loop30. The latter comprises a summing unit 40, a voltagecontrolledoscillator (VCO) 42 and a feedback loop comprising a variable frequencydivider 44 and a phase detector 46. Summing unit 40 controls thefrequency of VCO 42 in accordance with the sum of two DC voltages, oneproduced by the output of tachometer 38. The latter signal provides anapproximate or coarse frequency control for the VCO while the former,representing the phase difference between the VCO pulse train and thepulse train produced by the spark signal processor 24, represents thenormal phase error signal by which fine control of the phase-locked loopis achieved.

The system is so arranged that when operating properly, the output ofVCO 42 provides 3,600 pulses per engine revolution. The VCO output istherefore 900 times the spark frequency for an eight-cylinder engine,1,200 times the spark signal frequency for a sixcylinder engine, and1,800 times the spark frequency for a four-cylinder engine. A controlswitch 48, cooperating with divider 44, assures the proper frequencyrelationship between the two inputs to phase detector 46 for four, six,or eight-cylinder engines according to the position of the switch.

The output of VCO 42 is provided to timing computer 16 as hereinafterdescribed, and also to the pseudo damper pulse generator 32. Thiscomprises a sample pulse generating unit 50, a gating circuit 52, adigital delay unit 54 controlled by an advance-retard switch 56, a clockpulse generator 58, a counter 60, and a pulse rate selector 62,controlled by a switch 64.

Pseudo pulse generator 48 is described in detail below, but brieflystated, its function is to select particular ones of the 3,600 VCOpulses per engine revolution in accordance with the setting of acylinder selection switch 64 and to delay the selected pulses for apredetermined count depending on whether the engine is to be timed withthe spark plugs firing before or after the top dead center position ofthe piston (i.e. advance or retard operation, respectively.) The pulsesare selected to provide the required two, three, or four pulses perengine revolution for a four-cylinder, six-cylinder, or eight-cylinderengine, respectively. Also, the selected pulses are adjusted inaccordance with the previously noted degree spacing between the top deadcenter position of cylinder No. l and the position at which the dampernotch is sensed, and to provide the 45 degree calibration offset whichprevents cross-over error as previously described.

The averaging and timing computation functions are provided by timingcomputer subsystem 16. This includes an advance-retard logic unit 68, anaveraging logic unit count generator a main counting logic unit 72 and acalibration countgenerator 74. These cooperate under the control of asequencing logic unit 76 to provide a digital representation of theaverage of the angle between ignition and the top dead center positionof the piston for each cylinder. Ignition is represented by the outputof spark signal processor 24 while the associated top dead centerposition is keyed to the top dead center position of the No. 1 cylinder,with the succession of pseudo damper pulses being provided by the outputof digital delay unit 54. The average is taken over 128 firings, i.e.,16 complete cycles for an eightcylinder engine. The angular internal ismeasured by counting the number of VCO pulses between the ignition pulseand the associated pseudo pulse. Since the VCO provides 3,600 pulses perengine revolution, each pulse counted represents 0.1 degrees.

As will be appreciated, for an engine timed in the advance mode, thespark signal precedes the associated pseudo damper signal, while in theretard mode, the pseudo damper signal occurs first. Advance-retard logicunit 68 operates to select which of the two pulses defines the beginningof each counting inverval in accordance with the position of anadvance/retard selection switch 78.

During a succession of counting intervals, the number of VCO pulses isaccumulated, and divided by the number of counting intervals to beemployed in the averaging process. This is accomplished by averaginglogic unit 70. The resulting average count is provided to main countinglogic unit 72 which cooperates with calibration logic unit 74 tosubtract 450 counts (i.e., representing 45 degree offset employed toprevent cross-over error),after which the result is visually displayedby means of timing angle display unit 84.

RPM and timing limit computer 20 is comprised of a comparison logic unit88, target and tolerance count generators 90 and 92, a limit logic unit94, and an RPM limit setter 96. Comparison logic unit 88 provides ameasure of the difference between the actual average timing angle asindicated by the output of main counting logic unit 72, and a targettiming angle as indicated by unit 90, and provides signals indicatingwhether the difference is within a preset tolerance range established bytolerance count generator 92, or above or below the range. Limit logicunit 94 utilizes these signals to operate display 98, and also providesa comparison between the actual RPM as indicated by counter 82, and amaximum RPM suitable for timing measurement as indicated by limit setter96. A limit display 98 also provides an indication if the actual RMPexceeds the acceptable limit.

In addition, there is provided a printer unit 100, controlled bysequencing logic unit 76 by which a permanent record of the measuredtiming may be produced. The printout may include such reference data asthe date, the machine number, etc., as well as the timing angle and theRPM at the time of measurement (actually, the average RPM over themeasuring interval, as explained below). The latter data are provided bymain counting logic 72, and RMP counter 82. Control signals are providedby sequencing logic 76, fault detection circuit 34 and limit logic 94.Signals from the latter prevent printer operation if incorrect data issensed.

FIGS. 3 through 10, taken in conjunction with the waveform diagram shownin FIG. 2 illustrate in more detail the construction and operation of apreferred embodiment of the apparatus illustrated generally in FIG. 1.

Referring to FIG. 3 there is shown the construction of damper signalprocessor 22. The circuit comprises an integrated circuit differentialamplifier 101 (such as Motorola type MC 741, or equivalent) having itsinputs resistance coupled to damper pickup 26. The output of amplifier101 at pin 6 is coupled to an automatic level control unit 102 comprisedof a transistor Q1 and a detector circuit including diodes CR1 and CR2,capacitor C1 and resistor R1.

Transistor Q1 provides a current path for a differentiator circuitcomprised of a capacitor C2 and resistors R2 and R3 which couples theoutput of amplifier 101 to the base of a transistor Q2, the collector ofwhich is, in turn, RC coupled to the base of an output transistor Q3.

Referring now to FIG. 2, lines (a)(e), as well as FIG. 3, the dampernotch 104 [FIG. 2, line (a)] may be regarded as a shallow rectangularcut-out having a leading edge 106 and a trailing edge 108. As notch 104passes through the field of sensitivity of pickup 26, there is producedan output pulse such as illustrated in FIG. 2, line (b) having apositive-going leading edge 110 corresponding to the abrupt change inspacing between the pickup and the damper periphery as the lead ing edge106 of the notch passes into the field of sensitivity of the pickup. Asthe leading edge passes the pickup, the output peaks, and returns towardzero, reaching the level at about the time that the center of the notchpasses the pickup. Then, as the trailing edge of the notch approachesthe pickup,its output continues negative, and reaches a minimum value atabout the time that the trailing edge 108 passes the pickup. Thereafter,the output again becomes positivegoing, and returns to zero as the notchpasses beyond the pickup.

The purpose of damper signal processor 22 is to convert the waveformshown in FIG. 2, line (a) to a narrow pulse such as shown in FIG. 2,line (c), as near as possible to the center of the damper notch.

Returning to FIG. 2, damper notch pickup 26 is coupled through amplifier101 which inverts the pickup output, and at the same time converts it toa singleended signal referenced to ground. The result is shown in FIG.2, line(d). As this signal goes negative, it is rectified and smoothedby detector circuit 102. The resulting time varying DC signal operatestransistor Q1 which applies a negative bias level at the base of a transitor Q2 through resistors R2 and R3. Becuase of capacitor C2, theoutput of amplifier 101 is differentiated to produce a pulse shown inFIG. 2, line (e), superimposed on the depressed bias level for the baseof transistor Q2.

As will be understood, the negative bias creates an input threshold fortransistor Q2 which maintains the same nonconductive until the inputpulses [FIG. 2 line (e)] becomes sufficiently positive. By adjusting thethreshold level properly, the conduction period of transistor O2 isarrangedto occur very close to the zero crossing of the damper pickupoutput, i.e., at approximately the peak of the derivative waveform whichoccurs at the time thatthe center of the damper notch passes the pickup.1

With transistor Q2 nonconducting, transistor Q3 conducts, whereby thenormal level for the output signal is zero [see FIG. 2, line (c)]. Whentransistor Q2 conducts, transistor Q3 cuts off, thereby producing thesharp positive pulse at the center of the damper notch shown in FIG.2(c).

Referring to FIG. 2(f), there is shown the waveform sensed by sparkpickup 28 for each spark plug ignition. A cycle begins when the breakerpoints open producing a negative going transition indicated at 120.Thereaf ter, when the points close, a fairly complicated waveformcharacterizing the magnetic field resulting from the spark itselfoccurs. This is indicated at 122. Since the timing measurement is madewith reference to the opening of the points, it will be appreciated thatspark signal processor 24 must be responsive to the opening of thepoints, i.e. at 120, but preferably not tothe remainder of the waveform.

The circuitry required for accomplishing this result is shown in detailin FIG. 3. As illustrated, an input differential amplifier 124 such asone-half of a Motorola Type MC-l437, or the equivalent, is resistancecoupled to spark pickup 28. Amplifier 124 operates to invert thepolarity of the incoming spark signals, and at the same time to convertit to a singleended signal referenced to ground. The resulting output ofamplifierl24, at pin 2 is shown in FIG. 2( g). The inverter spark signalis coupled to the negative input of a second differential amplifier 126which may be the other half of the integrated circuit comprisingamplifier 124. As illustrated, the coupling circuit includes a capacitorC2 and a voltage divider comprising a pair of like resistors R4 and R5,coupled between the negative power supply and ground.

With the R4-R5 voltage divider connected to the negative power supply,it may be seen that a negativeoffset or bias is applied to the negativeinput of amplifier 126. With the positive input at pin 8 grounded, the

gine.

negative bias at pin 9 tends to drive the amplifier output at pin 12 toa high level, but to prevent this, there is provided a feedback diodeCR3 which clamps the output to approximately volts for all negativeinputs.

From the AC standpoint, the RC coupling circuit operates todifferentiate the spark waveform in FIG. 2( g) to produce a waveformsuch as shown in FIG. 2(h) including a sharp positive going spike 128coincident with the opening of the points. It will, however, be notedthat because of the negative offset produced by the voltage divider,only the portion of spike 128 exceeding the offset voltage reaches theinput of amplifier 126 as a positive level.

When the input to pin 9 of amplifier 126 exceeds the bias threshold, theamplifier operates to produce a negative output, and remains operativeuntil the input falls below the threshold. The result is astraight-sided negative pulse such as shown in FIG. 2(i), having aleading edge 130 coinciding with opening of the points.

The output of amplifier 126 is connected to the input of tachometercircuit 38, the construction of which is illustrated in FIG. 5. Inessence, tachometer circuit 38 comprises a single shot multi-vibratorgenerally denoted at 132, having an adjustable operating period, and anintegrator circuit 134 to produce a DC analog signal representative ofthe frequency of the ignition pulse train produced by spark signalprocessor 24.

Single shot 132 is comprised of a transistor Q4 and an amplifier 136,the latter comprising one-half of a Motorola Type MC-1437 integratedcircuit, or the equivalent. A feedback path from the output of amplifier136 at pin 12 is provided to the base of transistor Q4 over lead 138through a pair or resistors R7 and R8.

Timing control for single shot 132 is provided by a timing capacitor C4and a resistance circuit 140 including a series resistor R9 and threeparallel resistors R10, R11, and R12 coupled in common to resistor R9,and to the fixed contacts of cylinder selection switch 36. The values ofresistors R10 through R12 in relation to capacitor C4 and resistor R9are so chosen that the sum of the pulse widths at the output of thesingle shot over one engine revolution is independent of the number ofpulses. In other words, for a six-cylinder engine which produces threeignition pulses per revolution, the pulse width is two-thirds that for afour-cylinder engine which produces two ignition pulses per revolution.Correspondingly, for an eight-cylinder engine which produces fourignition pulses per revolution, the individual pulse width is one-halfthat for the four-cylinder en- The output of single shot 132 is providedas an input to phase detector 46 hereinafter described over lead 138,and also to an output circuit 141 comprising a transistor Q5, andassociated circuitry. The collector of the transistor provides the sparkoutput to timing computer subunit 16 (see FIG. 1) as described in detailbelow.

The output of single shot 132 also provides the input to VCO rangeintegrator 134. The latter comprises a differential amplifier 142,preferably the second half of the integrated circuit comprisingamplifier 136, provided with a feedback circuit including a capacitor C5to integrate the pulse train output of single shot 132.

A shunt diode CR7 controls the maximum amplitude of the ingegrator inputwhile a series diode CR6 blocks the passage of any positive signals. Theoutput at pin 2 is therefore a DC level representative of the enginespeed. Because the pulse width variation depending on the number ofcylinders as explained above, the integration performed by circuit 134is independent of the number of ignition pulses per engine revolution.

The output of amplifier 142 at pin 2 is coupled through an RC filtercircuit 144 as the VCO range control signal for phase-locked loop 30,illustrated in detail in FIG. 6. As shown, the input from tachometercircuit 38 is provided to an integrated circuit amplifier 146 comprisingsumming circuit 40 (see FIG. 1). The input at pin 9 serves as a summingjunction between the VCO range signal provided by a resistor R13 and bythe output of phase detector 46 hereinafter described provided through aresistor R14. The output of amplifier 146 is connected to the controlinput of the voltage controlled oscillator which preferably is comprisedof a commercially available integrated circuit unit such as theSignetics Type NE-556V, or its equivalent. The output at pin 3, having afrequency proportional to the amplitude of the control input at pin 5,is provided through an output amplifier comprising a transistor 06,which in turn feeds a pair of output circuits comprising furthertransistors Q7 and Q8. The output of transistor Q7 provides the VCOoutput signal to the timing computer subsystem hereinafter describedwhile transistor Q8 provides the input for divider 44 in the phaselockedloop feedback circuit.

As previously noted, the output of VCO 42 is controlled such that itsoutput frequency varies with engine speed to produce exactly 3,600pulses per engine revolution. As shown in FIG. 1, frequency control bymeans of phase detector 46 requires comparison of the output of sparksignal processor 24 with the output of VCO 42. Thus, it is necessary toreduce the frequency of the VCO output to correspond to that of thespark signal processor. Since the spark signal processor produces two,three, and four spark pulses per engine revolution for a four, six, andeight-cylinder engine respectively, and the VCO output is 3,600 pulsesper revolution, it will be appreciated that divider unit 44 must dividethe VCO output by 1,800 for a four-cylinder engine, by 1,200 for asix-cylinder engine, and by 900 for an eightcylinder engine.

The foregoing result is accomplished by employment of digital dividersand associated combinational logic including a divide by 300 unit 148connected in parallel to a divide by six unit 150 and a divide by fourunit 152. Each of the latter may be constructed in conventional fashionof commercially available ingegrated circuit counters. For example,divider 148 may be constructed of a series combination of two decadecounters such as Texas Instruments Type 7490 and a divide by 12 countersuch as Texas Instruments Type 7492 wired to provide a divide by threefunction. Similarly, divider 150 may be a Texas Instruments Type 7492counter wired to provide both a divide by six and divide by threefunctions. Divider 154 may be a Texas Instruments Type 7493 four bitbinary counter wired to provide the divide by four function.

Considering dividers 148 and 152 as connected in series, it may be seenthat the output of divider 152 effectively divides the output of VCO 42by 1,200. Similarly, considering dividers 148 and 150 as connected inseries, the divide by six output of divider 150 effectively divides theVCO output by 1,800 while the divide by three output divides the VCOoutput by 900.

Selection of the proper one of the outputs of dividers 150 and 152 isaccomplished by an AND gate 154 connected to the output of divider 152,and two additional AND gates 156 and 158 connected to the divide by six"and divide by three outputs respectively of divider unit 150. Theoutputs of all of AND gates 154, 156, and 158 are connected to a NORgate 159 to provide the output of the divider unit as a whole.

Control inputs for AND gates 154, 156, and 158 are provided respectivelythrough three inverters 160, 162, and 164 by switch control circuit 166comprising three resistors R16, R15, and R17 connected respectively tothe inputs of inverters 160 through 164 and in common to the positivepower supply. The inputs of each of in verters 160 through 164 are alsoconnected to the fixed contacts of selection switch 48. The movingcontact is grounded thereby providing a low level input to the selectedone of inverters 160 through 164 and high inputs to the other twoinverters. Since the outputs of the two unselected inverters are low,the corresponding ones of AND gates 154 through 158 are inhibited whilethe AND gate associated with the selected one of inverters 160 through164 is activated. Thus, depending on the position of switch 48, divider44 provides at the output of OR gate 159 a signal at two pulses perrevolution for a four-cylinder engine (3,600 divided by 1,800), threepulses per revolution for a six-cylinder engine (3,600 divided by 1,200)and four pulses per engine revolution (3,600 divided by 900) for aneight-cylinder engine.

The output of divider 44 is provided over lead 168 as one input to thephase detector unit 46 through an input transistor Q10, the other inputbeing provided through a transistor Q9 from single shot 132 intachometer 38 previously described. In essence, phase detector unit 46comprises a pair of variable frequency single shot multi-vibrators 170and 172, each arranged to convert the incoming pulses (at two, three orfour pulses per engine revolution) into a square wave at the inputfrequency. An analog phase detector circuit 174 compares the phases ofthe resulting square waves.

Considering first the variable period single shot 170 associated withthe spark signal input at transistor Q9, the two amplification stagesare provided by a transistor Q11 and an integrated circuit differentialamplifier 176. Feedback from'the pin 2 output of amplifier 176 isprovided over lead 178 and resistors R18 and R19 to the base oftransistor Q11. Timing control is provided by a capacitor C6 and acharge control transistor Ql3 operated by a diode-RC biasing controlcircuit 180 which compares the duration of the on and off portions ofthe single shot output cycle and adjusts the charging time for capacitorC6 to maintain the two portions equal. v

The above-described function is accomplished by a pair of polarizedintegrator circuits 182 and 184 coupled to the collector of single shottransistor Q11 by a resistor R20. Due to opposite polarization of diodesCR12 and CR13, integrator 182 responds only to one portion of the singleshot cycle while integrator 184 responds only to the other portion. Atthe end of a cycle, a difference in the integrated signal levelsindicates that the two portions of the single shot operating cycle arenot of equal duration.

This difference, if any, is measured between a pair of resistors R21 andR22. The signal at the junction point is fed back over lead 186 to thebase of transistor Q13. The latter also receives as a bias reference,the output As will be appreciated, potentiometer R23 is set to produce asquare wave output at some frequency trigger signal with zero feedbackover lead 186. Thus, for.

other trigger frequencies, the bias on lead 186 varies the currentthrough transistor Q13, and thus the charging current for capacitor C6,to maintain the active period of the single shot equal to half theperiod of the triggering pulses. The result, therefore, is a squarewavesignal at pin 2 of amplifier 176 whose frequency is equal to the pulserate of the incoming signal from tachometer 38.

The second single shot circuit 172 is comprised of a transistor Q12 andan integrated circuit amplifier 188 forming the other half of theintegrated circuit comprising amplifier 176, connected by a feedbackpath 190. Single shot 172 is associated with the divider output providedover lead 168 through transistor Q10. Timing control for single shot 172is provided by capacitor C7 and a charging current control transistorQ14 operated by a pair of diode-RC feedback circuits 192 and 194 likecircuits 182 and 184. These monitor the waveforms at the collector oftransistor Q12 and provide a signal on lead 196 representative of thedifference between the two portions of the single shot cycle. Areference potentiometer R24 functions in the same manner aspotentiometer R23. Changes in the bias level on lead 196 varies thecharging current for capacitor C7 through transistor Q14 to maintain thesingle shot as a squarewave.

The outputs of single shots and 172 are provided to the phase detectioncircuit 174. This comprises transistors Q15 and Q16, and a differentialamplifier 198 which provides an output at pin 2 in a form of a DC signalrepresenting the phase difference between the outputs of the singleshots. The phase difference signal is provided over lead 200 through apotentiometer R25 and previously mentioned resistor R14 to the summingjunction input of amplifier 146. Thus, it may be seen that the outputfrequency of VCO 42 is controlled by the sum of the VCO range signalprovided by tachometer 34 and the signal representing the phasedifference between the oscillator output and the spark pulse signalgenerated by single shot 132. The aforementioned arrangement isparticularly advantageous since ,it allows establishing a coarseadjustment for the VCO related directly to the engine RPM, and a fineadjustment based on the phase difference between the oscillator outputand the incoming spark pulses.

The VCO output is provided by previously men-- tioned transistor 07 overlead 202 to the input of pseudo pulse generator 48, illustrated indetail, along with digital delay unit 54, in FIG. 7.

Before proceeding with the structural description, however, it isworthwhile to recall the functional requirements for the pseudo pulsegenerator and associated digital delay unit. To eliminate thepossibility of cross-over error as described above, the timing systemherein described measures the timing angle with respect to a reference45 degrees before the top dead center position of the associatedcylinder for an engine operating in the retard mode, and 45 degreesafter the top dead center position of the associated cylinder for anengine operating in the advance mode.. Signals representing each ofthese angular positions are to be generated with reference to the singleactual pulse produced by the damper pulse sensor at a position 135degrees after the top dead center position for the cylinder No. 1.

Considering first the operation of a four-cylinder engine in the retardmode, the first pseudo damper pulse must appear 45 degrees before thetop dead center position for cylinder No. l and 180 degrees thereafter,i.e., at 225 degrees after top dead center for cylinder No. 1. Thisprovides pseudo damper pulses for two of the four cylinders; theremaining pseudo damper pulses are to be generated at the same angularpositions during the next revolution.

correspondingly, for a six-cylinder engine operating in the retard mode,pseudo damper pulses are required 45 degrees before top dead center forcylinder No. 1, and at 120 degree intervals thereafter, i.e., at 75 and195 degrees after top dead center for cylinder No. 1. Finally, for aneight-cylinder engine, four pseudo damper pulses per revolution must beprovided at 45 degress before top dead center for cylinder No. l, and atsuccessive 90 degree intervals, i.e., at 45, 135, 225, and 315 degreesbefore top deadcenter for cylinder No. 1.

Because the single reference pulse is available only at 135 degreesafter top dead center, it may be seen that pseudo damper pulses mayreadily be referenced to 135 degrees after top dead center for cylinderNo. 1, rather than to the top dead center position. The required pseudodamper pulse angles for retard operation, taking into account the 45degree offset to avoid cross-over erros, are listed below in TABLE ONE.The second column gives the angles with reference to top dead center,while the third column gives the angles with reference to the dampernotch.

*135" after TDC. No. 1.

TABLE ONE: PSEUDO PULSES FOR RETARD TIMING Considering now the situationfor operation in the advance mode, it will be appreciated that avoidanceof cross-over error for a timing angle preceding the top dead centerposition requires the appearance of the pseudo pulse 45 degrees aftertop dead center. Thus, for a four-cylinder engine, the pseudo damperpulses must appear at 45 and 225 degrees after top dead center forcylinder No. 1, or at 90 and 270 degrees with reference to the 135degrees offset between the sensing of the damper notch and top deadcenter for cylinder No. 1. Corresponding analysis shows that withrespect to the top dead center position for cylinder No. 1, pseudodamper pulses for a six-cylinder engine must appear at 45, 165, and 282degrees, or at 30, 150, and 270 degrees with reference to the dampernotch. For an eight-cylinder engine, with reference to top dead centerposition for cylinder No. l, damper pulses are required at 45, 135, 225and 315 degrees, corresponding to 0, 90, 180, and 270 degrees withreference to the damper notch. The foregoing results are summarized inTABLE II below.

No. of Advance Mode: Advance Mode: Cylinder (Ref. TDC No. 1) (Ref.Damper Notch) i 135 after TDC. No. 1

TABLE TWO: PSEUDO PULSES FOR ADVANCE TIMING Comparing TABLES I and II,it may be seen that in each case, a pseudo damper pulse for retard modetiming appears 90 degrees before the corresponding pseudo damper pulsefor advanced mode timing. (This fact may also be appreciated fromrecognition that avoidance of cross-over error requires positioning thepseudo damper pulse 45 degrees before top dead center for retard timingand 45 degrees after top dead center for advance timing, producing a net90 degree offset.) Because of this, and in viewof the availability ofthe reference pulse at 135 degrees, it is found convenient to generatethe pseudo damper pulses in relation to the damper notch according tothe angular positions set forth in the right hand column of TABLE I andto provide the corresponding pseudo pulses for advance timing bydelaying each of the retard mode pseudo damper pulses 90 degrees, i.e.,at the angular positions set forth in the right hand column of TABLE II.

The circuitry used to accomplish these functions is illustrated in FIG.7. The pseudo pulse generating unit 32 includes counter 60 comprised ofa four-decade binary coded decimal counter unit 204 constructed ofintegrated circuit units of any conventional or desired type. Counter204 receives as its count input, the output of a single shot 58comprising the clock pulse generator referred to in FIG. 1. The latterreceives as its input, the VCO output signal described above inconnection with FIG. 6. A reset input for counter 204 is provided byanother single shot 206 receiving as its input, the damper signalprovided by the output of transistor Q3 (see FIG. 3.) As will beappreciated, the VCO output constitutes a train of 3,600 pulses perengine revolution while the damper signal is pulse appearing once perrevolution. Thus, counter 204 reaches to a 1 count of 3,600 in binarycoded decimal form before being reset for each engine revolution.

The BCD outputs of counter 204 for the two least significant decades areprovided in binary coded decimal form to a one-counter intervalgenerator- 208, while the outputs for the two most significant decadesare provided respectively to a pair of BCD to 10-line decoders 210 and212. One-count interval generator 208-comprises an AND gate 214 coupleddirectly to the output for the least significant bit (0,1 degree) of thefirst decade, while the outputs for the remaining bits of the firstdecade are coupled through respective inverters 216, 218, and 220.Similarly, all four bits comprising the second decade are coupled to ANDgate 214 through inverters, two of which are shown at 222 and 224.Assuming counter 204 provides its outputs in a positive logic format,the inputs to AND gate 214 are all high only during the first count ofevery two decades, i.e., every 100 counts.

BCD to 10-line converters 210 and 212 are preferably constructed ofcommercially available integrated circuit units such as TexasInstruments Type 7442. Such units provide ten outputs in response to aBCD input. The output corresponding to the input code is low; all theother outputs are high.

Decoder 210 is associated with the third decade of counter 204, and thusswitches states every one hundred counts. Correspondingly, decoder 212is associated with the fourth decade of counter 204 and thus switchesstates only every one thousand counts. However, the available outputsfrom third decade decoder 210, only the 000, 600, 700, 800, and 900count outputs are required. From fourth decade decoder 212, only the0000, 1000, 2000, and 3000 count outputs are required.

Each of the above-mentioned outputs is provided through a respective oneof inverters 226(a) through 226(i) to convert the signals to positivelogic. Thus, the outputs of inverters 226(a) (i) are high between thevarious counts set forth below in TABLE III.

Inverter 226(b) 600-699,l60O-l699,et 226(c) 700-799,l700-l799,etc.226(d) R-899,l800-l899,etc. 226(e) 900-999,l900-l999,etc.

226(g) 1000-1999 226(h) 2000-2999 226(i) 300-3599 *Typical; repeatsevery I000 Counter resets at 3600 TABLE III The outputs of inverters226(a) (i) are connected to various ones of six AND gates 228-238comprising part of pulse selector 62. AND gates 228-238 function tocollect required ones of the hundred count signals and the thousandcount signals to form six different 100 count intervals. In particular,the outputs of inverters 226(a) and (f) are coupled to AND gate 228 toproduce a high output during counts 0-99. The outputs of inverters226(d) and 226(g) are coupled to AND gate 230 to produce a high outputfor counts 1,800-1,899. The outputs of inverters 226(e) and (f) areprovided to AND gate 232 to produce a high output for the counts900-999. The outputs of inverters 226(b) and 226(f) are produced to ANDgate 234 to produce a high output for the counts 600-699. The outputs ofinverters 226(c) and (h) are provided to AND gate 236 to produce a highoutput for counts 2,700-2,70l. Finally, the outputs of inverters 226(a)and 226(i) are coupled to AND gate 238 to produce a high output forcounts 3 ,000-3,099.

The outputs of AND gates 228 and 230 are coupled to the inputs of an ORgate 240. AND gates 228 and 230 are also coupled as'inputs to another ORgate 242, along with the outputs of AND gates 232 and 236. A third ORgate 244 receives as itsinputs, the outputs, of AND gates 230, 234, and238. OR gate 240 thus operates counts 0-99 and 1,800-1,899, while ORgate 242 operates for counts 0-99, 900-999, 1,800-1,899, and2,700-2,799. OR gate 244 operates for the counts of 600-699,1,800-1,899, and 3,000-3,099.

The outputs of OR gates 240, 242, and 244 are connected respectively asinputs to three AND gates 246, 248, and 250. Second inputs for each ANDgate 246 through 250 are provided through three inverters 252, 254, andand 256, the inputs of which are connected to the positive power supplythrough three resistors 258, 260, 262, respectively. Each resistor isalso connected to the fixed contacts of three-position switch 64 whichhas its moving contact grounded. As will be understood, resistors 258,260, and 262 maintain the inputs to inverters 252 through 256 at a highlevel except for the inverter attached to the grounded switch contact.Thus, the outputs of two of the inverters are low while the output ofthe selected inverter is high to activate the associated AND gate. Thus,with switch 64 in the four-cylinder position, AND gate 246 isconditioned, with switch 64 in the six-cylinder position, AND gate 248is conditioned and with switch 64 in the eightcylinder, position, ANDgate 250 is conditioned.

The third inputs to each of AND gates 246 through 250 are provided incommon over lead 264 by the output of AND gate 214. As previouslydescribed, AND gate 214 operates to provide a high level output for asingle count interval at the beginning of every counts. Thus, AND gate246 operates only at counts 0 and 1,800, AND gate 248 operates only atcounts 0, 900, 1,800, and 2,700, while AND gate 250 operates only atcounts 600, 1,800 and 3,000.

Recalling that a cycle for counter 240 begins upon receipt of a dampersignal (at which time the counter is reset through single shot 206) andthat each count pulse represents 0.1 degree after the damper pulse, itmay be seen that the pseudo pulses for a four-cylinder engine occur-at 0degrees and degrees after the damper pulse. Similarly, for aneight-cylinder engine, the pseudo damper pulses occur at 0, 90, 180, and270 degrees after the damper pulse. For a six-cylinder engine, thepseudo damper pulses occur at 60, I80 and 300 degrees after the damperpulse.

The outputs of AND gates 246-250 are coupled through an OR gate 266 toone input of AND gate 52 shown in FIGS. 1 and 7. The other input for ANDgate 52 is provided by a sample pulse generator 50 comprised of a singleshot 270 triggered by the VCO output on lead 202 through an inverter268.

The output of AND gate 52 provides the input for digital delay unit 54.This is essentially a three-decade coded decimal counter 272 andassociated decoding and steering logic. Counter 272' operates undercontrol of the VCO clock pulses provided through clock generator singleshot 58 over lead 298. The counter thus maintains a BCD countcorresponding to lOths, units, and 10s of degrees.

The BCD outputs of counter 272, in order of increasing significance, areconnected to respective BCD to 10 line decoders 274, 276 and. 278;Decoders 274, 276, and 278 are constructed identically to.previouslydescribed decoders 210 and 212, and provide a low level atthe output corresponding to the BCD value of the input. Only selectedones of the 10 available outputs are used, namely, the zeroandone-tenths outputs of decoder 274, the zero-units output of decoder.276, and the nine-tens output of decoder 278.

The aforementioned decoder outputs are connected through respectiveinverters 280(a)-280(e) as inputs to a pair of AND gates 282 and 284.Inverters 280(b), 280(c), and 280(d) are connected as inputs to AND gate282, while the outputs of inverters 280(a), 280(c), and 280(e) areconnected to AND gate 284. The control input for AND gate 284 isprovided directly over a lead 286, while the same signal, coupledthrough an inverter 288, provides the control input for AND gate 282.

' Lead 286fis connected to advance-retard unit 56 (also shown in FIG. 1)which comprises a resistor R26 coupled to the positive power supply, tolead 286, and

to one of the fixed contacts of a two-position switch 288, the othercontact of which is open, and the moving contact of which is grounded.The connected contact of switch 288 represents the retard mode ofoperation. Thus, with the switch in the retard position, the signal onlead 286 is low, inhibiting AND gate 284, and activating AND gate 282.Correspondingly, with switch 288 in the advance position, lead 286 ishigh, conditioning AND gate 284 and inhibiting AND gate 282.

From the above description of the interconnection between decoders274-278, inverters 280, and AND gates 282 and 284, it may be seen thatfor retard mode timing, AND gate 282 operates to provide a high input toOR gate 290 only when the count contained in decade counter 272 is 001,i.e., the minimum possible delay. For advance mode timing, AND gate 284provides a high input to OR gate 290 only when counter 272 is at a countof 900, i.e., a delay of 90 degrees.

Operation of counter 272 is controlled by the pseudo pulse output of ORgate 266 coupled through AND gate 52. The output of AND gate 52 isconnected to the set input of a set-reset flip-flop 292, the reset inputto which is provided through an AND gate 294. The latter receives as itsinputs the pseudo damper signal output of OR gate 290 and the samplepulse signal produced by single shot 270. The zero output of flip-flop292 is coupled over lead 296 to the reset input of counter 272.

' For a counter 272 constructed of three seriesconnecte'd TexasInstruments type SN-7490 decade units, the counter advances on anegative to positive transition of the clock signal, while a high levelat the reset input returns all of the outputs to zero. Thus, as long asflip-flop 292 is reset, its zero output is high and counter 272 is heldat a count of zero.

Upon arrival at an output from pseudo pulse generator 32, AND gate 52operates and sets flip-flop 292. The zero output of the flip-flop thengoes low,freeing counter 272 to advance in response to the clock pulseson lead 298. Decoders 274-278, inverters 280, and AND gate 282 providean output through OR gate 290 after a single advance of counter 272 forretard operation, while decoders 274-278, inverters 280, and AND gate284 provide an output through OR gate 290 after 900 counts (i.e., 90degrees) for advance mode operation. In either case, the output of ORgate 290 actuates AND gate 294 and resets flip-flop 292, therebyterminating the operation of counter 272. Since each pseudo pulsereactivates the counter by setting flip-flop 292, the result is a seriesof pulses delayed with respect to the output of the pseudo pulsegenerator, either by I count or 900 counts for retard or advance modeoperation, respectively.

One further point may be noted. Referring to Tables 1 and 2 above, itmay be seen that for an eight-cylinder engine, the advance and retardmode pseudo damper pulses coincide. Thus, delay of the pseudo pulsegenerator outputs for advance timing of an eight-cylinder engine is notactually pg,45 Actuation of the delay unit is therefore inhibited for aneight-cylinder engine by means of a diode CR14 connected to the junctionbetween lead 286 and resistor R26 and to the eightcylinder position ofselector switch 64 by means of lead 300. With switch 64 in theeight-cylinder position, lead 300 is grounded, which overrides theoperation of advance-retard switch 288 and assures the presence of a lowsignal level on lead 286.

Turning to FIG. 8, there is illustrated the important functional aspectsof advance-retard logic unit 68, averaging logic unit 70, main countinglogic unit 72, advance-retard switch 78, timing angle display unit 80,RPM counter unit 82, and RPM display unit 84.

As previously explained, timing is measured by counting the number ofVCO pulses (each of which corresponds to 0.1 degree) between a sparkpulse and the pseudo damper pulse for the associated cylinder. Forretard timing, the pseudo pulse initiates the counting interval and thespark pulse terminates the counting interval. Conversely, for advancetiming, the spark pulse initiates the counting interval and the pseudopulse terminates the counting interval.

As illustrated in FIG. 8, the counting interval is defined by aset-reset cycle flip-flop 302 formed of a pair of cross-coupled NORgates 304 and 306. F lip-flop 302 is set through a NAND gate 308 andreset through another NAND gate 310. The inputs to NAND gate 308 areprovided by a further pair of NAND gates 312 and 314, while the inputsto NAND gate 310 are provided by a pair of NAND gates 316 and 318. Thespark pulse from spark signal processer 24 provides one input to NANDgates 314 and 316, while the pseudo damper pulse signal from digitaldelay unit 54 provides an input to NAND gates 312 and 318. Controlinputs for NAND gates 312 and 316 are provided over lead 320; thissignal is high when the system is operating in the retard mode. Aseparate control signal is provides over lead 322 for NAND gates 314 and318; this signal is high when the system is operating in the advancemode.

The signal levels on leads 320 and 322 are controlled by advarlce-retardunit 78. This comprises a pair of inverters 324 and 326, the outputs ofwhich are respectively connected to leads 320 and 322 and the inputs ofwhich are connected to the positive power supply through separateresistors R27 and R28. Also connected to the inputs of inverters 324 and326, respectively, are the fixed retard and advance contacts of atwo-position switch 328, the moving contact of which is grounded. Whenswitch 328 is in the retard position, the output of inverter 324 ishigh, conditioning NAND gates 312 and 316. Conversely, with switch 328in the advance position, the signal on lead 322 is high, conditioningNAND gates 314 and 318.

NAND gates 308 and 310 operate as OR gates with inverted inputs, i.e.,provide a high output if either input is low. Thus, for retard modeoperation, flip-flop 302 is set through NAND gates 308 and 312 by thepseudo damper pulse and is reset through NAND gates 310 and 316 by thenext spark pulse. For advance operation, flip-flop 302 is set throughNAND gates 308 and 314 by the spark .pulse and is reset through NANDgates 310 and 318 by the succeeding pseudo damper pulse.

The one output of cycle flip-flop 302 is connected over lead 330 to afurther pair of NAND gates 332 and 334, control inputs for which areprovided respectively over leads 322 and 320. NAND gates 332 and 334 arecoupled to another NAND gate 336 which acts as an OR gate with invertedinputs and thus provides a high input to a further NAND gate 338whenever cycle flipflop 302 is set.

The other input to NAND gate 338 is provided over lead 340 by the VCOoutput signal from phase locked loop 30. The output of NAND gate 338 iscoupled to the advance input of a divide by 128 counter 342

1. In an engine timing apparatus for internal combustion engines, saidapparatus having means to generate a pulse coincident with each ignitionof the engine being timed, means to generate a master pulse train havinga constant number of pulses per engine revolution, each pulserepresenting a fraction of said engine revolution, and means to generatea succession of reference pulses establishing a predetermined angularposition away from top dead center of each piston, measured in relationto rotation of the engine crankshaft, there being one reference pulsefor each piston ignition over each cycle of ignition firings; a timingcomputer, said timing computer comprising: means for establishing atiming interval between an ignition pulse and an associated referencepulse, said timing interval establishing means comprising means forproducing a train of timing pulses with each timing pulse being definedby an ignition pulse and a reference pulse; gating means receiving saidmaster pulse train, and being operative during said timing interval toprovide said master pulse train at the output thereof; a main counter;means coupling the output of said gating means to the input of said maincounter; a timing angle readout unit including data storage meanscoupled to the output of said main counter, and means for providing avisual display of the data contained in said storage means; controlmeans to operate said main counter for a predetermined interval andthereafter to actuate said angle readout means and to reset said maincounter, said control means comprising means for counting the number oftiming intervals, means coupled to the output of said counting means andresponsive to passage of at least one timing interval to generate acontrol signal, means responsive to generation of said control signalfor actuating said storage means to store the count contained in saidmain counter at that time, and further means responsive to generation ofsaid control signal for resetting said main counter after the datatherein has been transferred to said storage means, said means forestablishing said timing interval comprising a logic circuit having afirst input receiving said reference pulses, and a second inputreceiving said ignition pulses; selection means for establishing retardand advance modes of operation; said logic circuit being responsive toselection of the advance mode to initiate a timing interval in responseto an ignition pulse, and to terminate said timing interval in responseto the next reference pulse, said logic means being further responsiveto selection of the retard mode of operation to initiate a timinginterval in response to a reference pulse, and to terminate said timinginterval in response to the next ignition pulse, said logic circuitincluding a set-reset flipflop; means responsive to selection of theadvance mode of operation for coupling said ignition pulses to the setinput of said flip-flop, and the reference pulses to the reset input ofsaid flip-flop, and further being responsive to selection of the retardmode for coupling the reference pulses to the set input of saidflip-flop, and the ignition pulses to the reset input of said flip-flop;said logic further including means for coupling one output of saidflip-flop to said gating means to actuate the same when said flip-flopis set.
 2. A timing computer as defined in claim 1 wherein said controlcounting means comprises a counter, and means for operating said counterin response to transition of said flip-flop from the set to the resetcondition.
 3. In an engine timing apparatus for internal combustionengines, said apparatus having means to generate a pulse coincident witheach ignition of the engine being timed, means to generate a masterpulse train having a constant number of pulses per engine revolution,each pulse representing a fraction of said engine revolution, and meansto generate a succession of reference pulses establishing apredetermined angular position away from top dead center of each piston,measured in relation to rotation of the engine crankshaft, there beingone reference pulse for each piston ignition over each cycle of ignitionfirings; a timing computer, said timing computer comprising: means forestablishing a timing interval between an ignition pulse and anassociated reference pulse, said timing interval establishing meanscomprising means for producing a train of timing pulses with each timingpulse being defined by an ignition pulse and a reference pulse; gatingmeans receiving said master pulse train, and being operative during saidtiming interval to provide said master pulse train at the outputthereof; a main counter; means coupling the output of said gating meansto the input of said main counter; a timing angle readout unit includingdata storage means coupled to the output of said main counter, and meansfor providing a visual display of the data contained in said storagemeans; control means to operate said main counter for a predeterminedinterval and thereafter to actuate said angle readout means and to resetsaid main counter, said control means comprising means for counting thenumber of timing intervals, means coupled to the output of said countingmeans and responsive to passage of at least one timing interval togenerate a control signal, means responsive to generation of saidcontrol signal for actuating said storage means to store the countcontained in said main counter at that time, and further meansresponsive to generation of said control signal for resetting said maincounter after the data therein has been transferred to said said storagemeans, said control means including calibrating means responsive topassage of a predetermined number of timing intervals to reduce thecount stored in said main counter by a number corresponding to theangular position of said reference pulses in relation to top dead centerfor the associated piston.
 4. A timing computer as defined in claim 3further including a calibration counter, means responsive to saidcontrol signal to establish a calibration interval; gating meanscoupling said master pulse train to the input of said calibrationcounter, said gating means being operative during said calibrationinterval to pass said master pulses to said calibration counter; meansfor reducing the count in said main counter in synchronism with theoperation of said calibration counter; means responsive to apredetermined count in said calibration counter to terminate saidcalibration interval; means responsive to termination of saidcalibration interval to reset said calibration counter, whereby thecount in said main counter is reduced by said predetermined number.
 5. Atiming computer as defined in claim 4 further including means responsiveto establishment of said calibration interval to inhibit theestablishment of further timing intervals until said calibrationinterval is completed.
 6. In an engine timing apparatus for internalcombustion engines, said apparatus having means to generate a pulsecoincident with each ignition of the engine being timed, means togenerate a master pulse train having a constant number of pulses perengine revolution, each pulse representing a fraction of said enginerevolution, and means to generate a succession of reference pulsesestablishing a predetermined angular position away from top dead centerof each piston, measured in relation to rotation of the enginecrankshaft, there being one reference pulse for each piston ignitionover each cycle of ignition firings; a timing computer, said timingcomputer comprising: means for establishing a timing interval between anignition pulse and an associated reference pulse, said timing intervalestablishing means comprising means for producing a train of timingpulses with each timing pulse being defined by an ignition pulse and areference pulse; gating means receiving said master pulse train, andbeing operative during said timing interval to provide said master pulsetrain at the output thereof; a main counter; means coupling the outputof said gating means to the input of said main counter; a timing anglereadout unit including data storage means coupled to the output of saidmain counter, and means for providing a visual display of the datacontained in said storage means; control means to operate said maincounter for a predetermined interval and thereafter to actuate saidangle readout means and to reset said main counter, said control meanscomprising means to counting the number of timing intervals, meanscoupled to the output of said counting means and responsive to passageof at least one timing interval to generate a control signal, meansresponsive to generation of said control signal for actuating saidstorage means to store the count contained in said main counter at thattime, and further means responsive to generation of said control signalfor resetting said main counter after the data therein has beentransferred to said storage means, said control counting meanscomprising a second counter; means responsive to occurrence of a timinginterval to increase the count in said second counter; means responsiveto said second counter reaching a predetermined count indicatingoccurrence of the corresponding number of counting intervals for saidmain counter to generate said control signal; means responsive to saidcontrol signal and to said master pulse train to generate a secondcontrol signal a predetermined number of master pulses thereafter, andto generate a third control signal a predetermined number of masterpulses after said second control signal; means for coupling said secondcontrol signal to actuate said angle readout storage means; and Meansresponsive to said third control signal for resetting said main counter.7. A timing computer as defined in claim 6 wherein said means togenerate said second and third control signals comprises a thirdcounter, means for coupling said master pulse train to operate saidthird counter, and means responsive to said first control signal toreset said third counter.
 8. A timing computer as defined in claim 7wherein said means coupling said master pulse train to said thirdcounter comprises a frequency divider having a counter base sufficientlylarge that the complete operating cycle of said third counter is shorterthan the operating cycle for said second counter.
 9. A timing computeras defined in claim 7 further including calibration means responsive tosaid control signal to reduce the count stored in said main counter by anumber corresponding to the angular position of said reference pulses inrelation to top dead center for the associated piston.
 10. A timingcomputer as defined in claim 9 wherein said calibration means comprisesa fourth counter; means responsive to said control signal to establish acalibration interval; gating means coupling said master pulse train tothe input of said fourth counter, said gating means being operativeduring said calibration interval to pass said master pulse train to saidfourth counter; means for reducing the count in said main counter insynchronism with the operation of said fourth counter; means responsiveto a predetermined count in said fourth counter to terminate saidcalibration interval; and means responsive to termination of saidcalibration interval to reset said fourth counter.
 11. A timing computeras defined in claim 10 further including means responsive toestablishment of said calibration interval to prevent the establishmentof further timing intervals for said main counter, and to inhibitoperation of said third counter until said calibration interval has beenterminated.
 12. A timing computer as defined in claim 11 wherein saidthird counter is operative to generate said second control signal apredetermined number of counts after operation thereof is permitted toresume after termination of said calibration interval.
 13. In an enginetiming apparatus for internal combustion engines, said apparatus havingmeans to generate a pulse coincident with each ignition of the enginebeing timed, means to generate a master pulse train having a constantnumber of pulses per engine revolution, each pulse representing afraction of said engine revolution, and means to generate a successionof reference pulses establishing a predetermined angular position awayfrom top dead center of each piston, measured in relation to rotation ofthe engine crankshaft, there being one reference pulse for each pistonignition over each cycle of ignition firings; a timing computer, saidtiming computer comprising: means for establishing a timing intervalbetween an ignition pulse and an associated reference pulse, said timinginterval establishing means comprising means for producing a train oftiming pulses with each timing pulse being defined by an ignition pulseand a reference pulse; gating means receiving said master pulse train,and being operative during said timing interval to provide said masterpulse train at the output thereof; a main counter; means coupling theoutput of said gating means to the input of said main counter; a timingangle readout unit including data storage means coupled to the output ofsaid main counter, and means for providing a visual display of the datacontained in said storage means; control means to operate said maincounter for a predetermined interval and thereafter to actuate saidangle readout means and to reset said main counter, said control meanscomprising means for counting the number of timing intervals, meanscoupled to the output of said counting means and responsive to passageof at least one timing interval to generate a control signal, meansresponsive to generation of Said control signal for actuating saidstorage means to store the count contained in said main counter at thattime, and further means responsive to generation of said control signalfor resetting said main counter after the data therein has beentransferred to said storage means, and further including engine speedcomputing means; limit logic to establish a maximum acceptable enginespeed; means responsive to the sensing of an engine speed exceeding thepreset limit to generate a limit signal; and means responsive to saidlimit signal to disable said timing angle readout unit.
 14. A timingcomputer as defined in claim 13 wherein said engine speed computingmeans comprises a counter, means coupling said master pulse train tooperate said counter; engine speed readout means comprising means forstoring a count contained in said engine speed counter, and visualdisplay means for said stored count; clock means for producing aperiodic signal defining an engine speed computation interval; meansresponsive to the end of a computation cycle to generate a furthercontrol signal; means responsive to said first control signal foroperating said storage means to store the count then contained in saidengine speed counter; further means responsive to said further controlsignal to generate an additional control signal a predetermined timethereafter; and means responsive to said additional control signal toreset said engine speed counter.
 15. A timing computer as defined inclaim 14 wherein said coupling means comprises a frequency divider, thecounting base of said divider and the duration of said computinginterval being so selected in relation to the number of master pulsesper engine revolution that the count contained in said speed counter atthe end of the computation interval is equal to the average engine speedin RPM during the computing interval.
 16. A timing computer as definedin claim 14 wherein said limit logic comprises first circuit meanscoupled to said engine speed counter, a plurality of set-resetflip-flops, said first circuit means being operative to set saidflip-flops in a predetermined order as the count in said speed counterincreases by predetermined increments whereby, at the end of saidcomputation interval one or more flip-flops are set indicating thenumber of incremental advances of said engine speed counter during saidcomputation interval; latching means having individual latch circuitsconnected to the outputs of respective ones of said flip-flops; saidlatch circuits being responsive to said further control signal to storerespective signals indicative of the states of the associated flip-flopat that moment; means responsive to said additional control signals toreset said flip-flops; sensing means responsive to a particular signallevel stored in a latch circuit indicating that the associated flip-flophas been set; limit selection means for connecting said sensing means tothe output of a particular one of said latch circuits thereby selectingthe engine speed range at or above which said sensing means is operativeto generate said limit signal.
 17. A timing computer as defined in claim13 wherein said limit logic comprises multistate means coupled to saidengine speed computer, and operative to assume a predetermined one ofits states in correspondence to the computed RPM falling within one of asuccession of incremental ranges; limit selection means for establishingone of said states as corresponding to an excessive engine speed; meansfor sensing when said selected state has been reached, and operativethereupon to generate said limit signal for inhibiting said anglereadout.
 18. A timing computer as defined in claim 13 further includingangle range computation means comprising means for selecting target andtolerance values for the timing angle; means for comparing the count insaid main counter with the range established by said target andtolerance values, and logic means to generate a first signal indicativethat said acTual count exceeds the maximum acceptable value, a secondsignal indicating that said actual count is within the selectedtolerance range, and a third signal indicating that said count is belowsaid lower tolerance limits.
 19. A timing computer as defined in claim18 wherein said angle range computing means comprises first and secondcomputation counters; means to enter a count in said first and secondcounters corresponding to the selected target angle; means to increasethe count in said first counter by a count equal to the selectedtolerance, means to decrease the count in the second counter by a numberof counts corresponding to the selected tolerance; a first comparatorcoupled to said main counter and to said first computation counter; asecond comparator coupled to said main counter and to said secondcomputation counter; and logic means coupled to said first and secondcomparators to provide said first indication if the count in said maincounter exceeds that in the first computation counter, to provide saidsecond indication if the count in said main counter is less than orequal to the count in said first computation counter and is greater thanor equal to the count in said second computation counter, and said thirdindication if the count in said main counter is less than that in secondcomputation counter.
 20. A timing computer as defined in claim 19further including means to preset said main counter and said first andsecond computation counters to a reference count such that the totalcount in said second computation counter, including said reference countplus the difference between said target count and said tolerance count,does not fall below zero.
 21. An averaging computer for an internalcombustion engine timing apparatus, said apparatus having means togenerate a pulse coincident with each ignition of the engine beingtimed, means to generate a master pulse train having a constant numberof pulses per engine revolution, each pulse representing a fraction ofsaid engine revolution, and means to generate a succession of referencepulses establishing a predetermined angular position away from top deadcenter of each piston, measured in relation to rotation of the enginecrankshaft, there being one reference pulse for each piston ignitionover each cycle of ignition firings; said averaging computer comprising:means for establishing a timing interval between an ignition pulse andan associated reference pulse, said timing interval establishing meanscomprising means for producing a train of timing pulses with each timingpulse being defined by an igntion pulse and referencepulse; gating meansreceiving said master pulse train, and being operative during saidtiming interval to provide said master pulse train at the outputthereof; a main counter; means coupling the output of said gating meansto the input of said main counter, said coupling means comprisingfrequency division means having a division base N; a timing anglereadout unit including data storage means coupled to the output of saidmain counter, and means for providing a visual display of the datacontained in said storage means; and control means for said averagingcomputer, said control means comprising means for counting the number oftiming intervals, means coupled to the output of said counting means andresponsive to passage of a total of N timing intervals to generate acontrol signal, means responsive to generation of said control signalfor actuating said storage means to store the count contained in saidmain counter at that time, and further means responsive to generation ofsaid control signal for resetting said main counter after the datatherein has been transferred to said storage means; said number N beingin excess of the number of cyclinders in the engine being timed; wherebythe count transferred to said storage means represents the averagenumber of fractional parts of an engine revolution contained in thepreviously measured N timing intervals.
 22. A timiNg computer as definedin claim 21 wherein said number N is an integral multiple of the numberof cylinders in the engine being timed.
 23. A timing computer as definedin claim 21 wherein said control means includes calibrating meansresponsive to passage of a predetermined number of timing interals toreduce the count stored in said main counter by a number correspondingto the angular position of said reference pulses in relation to top deadcenter for the associated piston.
 24. A timing computer as defined inclaim 21 further including engine speed computing means; limit logic toestablish a maximum acceptable engine speed; means responsive to thesensing of an engine speed exceeding the preset limit to generate alimit signal; and means responsive to said limit signal to disable saidtiming angle readout unit.
 25. A timing computer as defined in claim 24wherein said limit logic comprises multistate means coupled to saidengine speed computer, and operative to assume a predetermined one ofits states in correspondence to the computed RPM falling within one of asuccession of incremental ranges; limit selection means for establishingone of said states as corresponding to an excessive engine speed; meansfor sensing when said selected state has been reached, and operativethereupon to generate said limit signal for inhibiting said anglereadout.
 26. A timing computer as defined in claim 21 further includingangle range computation means comprising means for selecting target andtolerance values for the timing angle; means for comparing the count insaid main counter with the range established by said target andtolerance values, and logic means to generate a first signal indicativethat said actual count exceeds the maximum acceptable value, a secondsignal indicating that said actual count is within the selectedtolerance range, and a third signal indicating that said count is belowsaid lower tolerance limits.
 27. A timing computer as defined in claim21 wherein said means for establishing said timing interval comprisesselection means for establishing retard and advance modes of operation;a set-reset flip-flop; logic means responsive to selection of theadvance mode of operation for coupling the ignition pulses to the setinput of said flip-flop, and the reference pulses to the reset input ofsaid flip-flop, said logic means further being responsive to selectionof the retard mode for coupling the reference pulse to the set input ofsaid flip-flop, and the ignition pulses to the reset input of saidflip-flop; means for coupling one output of said flip-flop to saidgating means to actuate the same when said flip-flop is set.
 28. Atiming computer as defined in claim 27 wherein said interval countingmeans comprises an N-bit counter; means responsive to transition of saidset-reset flip-flop to its reset condition to increase the count in saidN-bit counter by one bit; means responsive to said interval counterreaching a count of N to generate said control signal; a third counter,means for coupling said master pulse train to operate said thirdcounter; means coupled to said third counter, and responsive toparticular count states thereof to generate second and third controlsignals at predetermined intervals after said first control signal;means for coupling said second control signal to actuate said anglereadout storage means; means responsive to said third control signal forresetting said main counter, and means responsive to said first controlsignal to reset said third counter.
 29. A timing computer as defined inclaim 28 further including calibration means responsive to said firstcontrol signal, said calibration means comprising a fourth counter;means responsive to said first control signal to establish a calibrationinterval; gating means coupling said master pulse train to the input ofsaid fourth counter, said gating means being operative during saidcalibration interval to pass said master pulse train to said fourthcounter; means for reducing the count in said main counter insynchronism with the operation of said fourth counter; means responsiveto a predetermined count in said fourth counter corresponding to theangular position of said reference pulses in relation to top dead centerfor the associated piston to terminate said calibration interval; meansresponsive to termination of said calibration interval to reset saidfourth counter, and means responsive to establishment of saidcalibration interval to prevent operation of said set-reset flip-flop,thereby preventing establishment of intervals for said main counterduring said calibration interval, and further means to prevent operationof said third counter during said calibration interval.
 30. A timingcomputer as defined in claim 21 further including engine speed computingmeans comprising an engine speed counter; frequency division meanscoupling said master pulse train to operate said engine speed counter;engine speed readout means comprising means for storing a countcontained in said engine speed counter, and visual display means forsaid stored count; clock means for producing a periodic signal definingan engine speed computation interval; means responsive to the end of acomputation cycle to generate a further control signal; means responsiveto said further control signal for operating said storage means to storethe count then contained in said engine speed counter; means responsiveto said further control signal to generate an additional control signala predetermined time thereafter; and means responsive to said additionalcontrol signal to reset said engine speed counter, the counting base ofsaid frequency divider and the duration of said computing interval beingso selected in relation to the number of master pulses per enginerevolution that the count contained in said speed counter at the end ofthe computation interval is equal to the average engine speed in RPMduring the computing interval.
 31. A timing computer as defined in claim30 further including a limit logic for establishing a maximum acceptableengine speed, comprising first circuit means coupled to said enginespeed counter, a plurality of set-reset flip-flops, said first circuitmeans being operative to set said flip-flops in a predetermined order asthe count in said speed counter increases by predetermined incrementswhereby, at the end of said computation interval one or more flip-flopsare set indicating the number of incremental advances of said enginespeed counter during said computation interval; latching means havingindividual latch circuits connected to the outputs of respective ones ofsaid flip-flops; said latch circuits being responsive to said furthercontrol signal to store respective signals indicative of the state ofthe associated flip-flop at that moment; means responsive to saidadditional control signals to reset said flip-flops; sensing meansresponsive to a particular signal level stored in a latch circuitindicating that the associated flip-flop has been set to generate alimit signal; selection means for connecting said sensing means to theoutput of a particular one of said latch circuits thereby selecting theengine speed range at or above which said sensing means is operative togenerate said limit signal; and means responsive to said limit signal todisable said timing angle readout unit.
 32. A timing computer as definedin claim 21 further including angle range computing means comprisingfirst and second computation counters; means to enter a count in saidfirst and second counters corresponding to a selected target timingangle; means to increase the count in said first counter by a countequal to a selected tolerance angle; means to decrease the count in thesecond counter by a number of counts corresponding to the selectedtolerance; a first comparator coupled to said main counter and to saidfirst computator counter; a second comparator coupled to said maincounter and to said second compuation counter; and lOgic means coupledto said first and second comparators to provide a first indication ifthe count in said main counter exceeds that in the first computationcounter, to provide a second indication if the count in said maincounter is less than or equal to the count in said first computationcounter and is greater than or equal to the count in said secondcomputation counter, and a third indication if the count in said maincounter is less than that in second computation counter.
 33. A timingcomputer as defined in claim 32 further including means to preset saidmain counter and said first and second computation counters to areference count such that the total count in said second computationcounter, including said reference count plus the difference between saidtarget count and said tolerance count, does not fall below zero.